High-speed communication devices are equipped with transceivers for transmitting and receiving signals, and a serializer/de-serializer (hereinafter, SerDes) capable of converting parallel input to serial output and/or converting serial input to parallel output has been widely used in transceivers of high-speed communication devices.
FIG. 1 is a schematic diagram illustrating blocks in a multi-lanes SerDes transceiver. A multi-lanes SerDes transceiver implies that a transceiver having multiple pairs of transmitters and receivers. In FIG. 1, a 4-lines SerDes transceiver 10 is shown.
Each of the transmitters (Tx) 11 and the receivers (Rx) 13 needs a clock signal for their operations. However, providing separate clock generators at each of the transmitters 11 and receivers 13 consumes numerous space and power. Thus, a centralized clock source 15 generating a single clock signal sCLKin being collectively used by the transmitters 11 and the receivers 13 is provided. The clock source 15 can be, for example, a phase-locked loop (hereinafter, PLL) circuit.
After being generated, the single clock signal sCLKin is distributed to each of the transmitters 11 and the receivers 13. At the transmitters 11 and the receivers 13, the single clock signal sCLKin needs to be converted into a differential clock signal dCLKout.
FIG. 2 is a schematic diagram showing the differential clock generator. The differential clock generator 17 has a single input node and two differential output nodes. Through the single input node, the differential clock generator 17 receives the single clock signal sCLKin. Then, the single clock signal sCLKin is converted to two output clock signals Sout, Sout′. The differential clock signal dCLKout is defined as the difference between the output clock signals Sout, Sout′.
In FIG. 2, an exemplary pulse of the single clock signal sCLKin having a rising edge and a falling edge is used to demonstrate the operation of the differential clock generator. In the specification, transitions of the output clock signal Sout and those of the single clock signal sCLKin are assumed to be consistent. On the other hand, transitions of the output clock signal Sout′ and those of the single clock signal sCLKin are assumed to be opposite.
Ideally, the rising edge of the output clock signal Sout is aligned with the falling edge of the output clock signal Sout′, and the falling edge of the output clock signal Sout is aligned with the rising edge of the output clock signal Sout′. However, for a conventional differential clock generator, such alignment relationship can barely be achieved because of the following reasons.
As mentioned above, each of the transmitters 11 and the receivers 13 needs to be equipped with a differential clock generator. However, when the number of transmitters 11 and the receivers 13 increases, the distances d1, d2 between the clock source 15 and the transmitters 11 and the receivers 13 become longer. For example, the distances d1, d2 might be longer than 1 mm for a 4-lanes SerDes transceiver.
After being transmitted for the distances d1, d2, the quality of single clock signal sCLKin can be seriously affected. Consequentially, the operation of the differential clock generator 17 is influenced, and precisions of the output clock signals Sout, Sout′ degrade. Furthermore, a variation of the process, voltage, and temperature (hereinafter, PVT) parameters may bring side effects to the differential clock generator 17 so that precisions of the output clock signals Sout, Sout′ are affected. Thus, undesired characters of the output clock signals Sout, Sout′, such as skew and the duty-cycle distortion, might occur.
For the high frequency application, the cycle of the single clock signal sCLKin is relatively short and tolerance margin of the output clock signals Sout, Sout′ becomes more limited. Therefore, the capability of ensuring precisions of the output clock signals Sout, Sout′ becomes a critical issue, especially for the SerDes transceiver targeting to the high-frequency application.